From 781dd2de230e37e1dc05c992936125655fdf842f Mon Sep 17 00:00:00 2001 From: Efraim Flashner Date: Sun, 20 Feb 2022 12:30:17 +0200 Subject: gnu: postgresql-13: Fix building on riscv64-linux. * gnu/packages/databases.scm (postgresql-13)[arguments]: Add phase when buidling for riscv64-linux to apply a patch. [native-inputs]: When building for riscv64-linux add patch and patch file. * gnu/packages/patches/postgresql-riscv-spinlocks.patch: New file. * gnu/local.mk (dist_patch_DATA): Register it. --- .../patches/postgresql-riscv-spinlocks.patch | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 gnu/packages/patches/postgresql-riscv-spinlocks.patch (limited to 'gnu/packages/patches') diff --git a/gnu/packages/patches/postgresql-riscv-spinlocks.patch b/gnu/packages/patches/postgresql-riscv-spinlocks.patch new file mode 100644 index 0000000000..984a573642 --- /dev/null +++ b/gnu/packages/patches/postgresql-riscv-spinlocks.patch @@ -0,0 +1,41 @@ +https://www.postgresql.org/message-id/dea97b6d-f55f-1f6d-9109-504aa7dfa421@gentoo.org + +The attached patch adds native spinlock support to PostgreSQL on RISC-V +systems. As suspected by Richard W.M. Jones of Red Hat back in 2016, the +__sync_lock_test_and_set() approach applied on arm and arm64 works here +as well. + + +Tested against PostgreSQL 13.3 on a physical rv64gc system (BeagleV +Starlight beta board) - builds and installs fine, all tests pass. From +what I can see in gcc documentation this should in theory work on rv32 +(and possibly rv128) as well, therefore the patch as it stands covers +all RISC-V systems (i.e. doesn't check the value of __risc_xlen) - but I +haven't confirmed this experimentally. + +--- a/src/include/storage/s_lock.h ++++ b/src/include/storage/s_lock.h +@@ -315,12 +315,12 @@ + #endif /* __ia64__ || __ia64 */ + + /* +- * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available. ++ * On ARM, ARM64 and RISC-V, we use __sync_lock_test_and_set(int *, int) if available. + * + * We use the int-width variant of the builtin because it works on more chips + * than other widths. + */ +-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) ++#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv) + #ifdef HAVE_GCC__SYNC_INT32_TAS + #define HAS_TEST_AND_SET + +@@ -337,7 +337,7 @@ + #define S_UNLOCK(lock) __sync_lock_release(lock) + + #endif /* HAVE_GCC__SYNC_INT32_TAS */ +-#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ ++#endif /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */ + + + /* S/390 and S/390x Linux (32- and 64-bit zSeries) */ -- cgit v1.2.3